Successful Presentations at ISC '17

(Picture: JARA-HPC Booth at ISC17)

At this year's International Supercomputing Conference (ISC) exhibition from June 18 - 22, 2017 in Frankfurt, scientists of JARA-HPC presented flapAssist, an immersive Virtual Reality support for a factory layout planning process. In the interactive exhibit, the visitors of the booth were able to freely explore a virtual factory floor while a variety of visualizations, metrics, and interaction techniques for layout analysis, virtual walkthroughs, information visualization as well as annotation support, were demonstrated by Martin Bellgardt. The overall responses were positive, even though most visitors were not involved in factory planning activities. However, as flapAssist requires the Intel Threading Building Blocks (TBB) on shared-memory systems to ensure real-time interactions by means of an efficient parallelization, the exhibit was of high interest to the HPC community. Furthermore, it raised awareness of Virtual Reality as a way to interactively explore data in an immersive way.

Besides the exhibition, we were also involved in this year's conference program: Tom Vierjahn co-organized the 2nd ISC Workshop "WOIV’17: In Situ Visualization: Introduction & Applications". More than 30 researchers and practitioners attended 5 international paper talks and discussed the presented ideas. The workshop was framed by two keynotes: Intel's Jim Jeffers and TACC's Paul Navratil presented results of the latest IXPUG Software-Defined Visualization Workshop. Sandia's Ken Moreland discussed in detail "Why you don't want to do in situ visualization, and why you have to." The co-organizers are looking forward to continuing this workshop series at next year's ISC.

(Picture: JARA-HPC presentation)

(Picture: Visitor exploring the virtual factory.)
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